Recently, digital phase-locked loops (DPLLs) have gained a lot of popularity, and may provide a number of benefits over their analog counterparts, for instance in deep-submicron technologies. Digital-to-time converters (DTCs) can be used in DPLLs to compensate for the limited range of time-to-digital converters (TDCs) which can form part of the DPLL. In some implementations, integer multiples of a reference frequency can be synthesized, while in other implementations, non-integer multiples of the reference frequency can be synthesized.
A TDC can be implemented as a chain of flip-flops, which all sample a slightly delayed version of an input signal, each flip-flop comprising a tap or a section of a tapped delay line. Delays can be in the 10 ps range in order to minimize the quantization noise, and, can cause the chain to be very long (of the order of hundreds of ps) in order to cover one high-frequency clock period. When the DPLL is locked, edge positions of the high-frequency clock (often referred to as a digital crystal oscillator or “DCO”) period can be predicted very accurately, resulting in a minimal variation around these edge positions. However, in practice, the length of the chain of flip-flops forming the TDC can be limited to a few taps or sections, for example 16 taps, and the DTC can be implemented to delay the reference edge to the middle of the TDC. However, the design of the DTC for such applications can be challenging as the output may need to be very linear with low noise in order to provide a reference path through the DPLL.
In an article entitled “1.3V 20 ps Time-to-Digital Converter for Frequency Synthesis in 90-nm CMOS” by Robert Bogdan Staszewski et al., IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, Vol. 53, No. 3, March 2006, a “pseudodifferential TDC architecture” is described which can be used in all-digital fractional-N PLLs. A TDC core is implemented as a phase/frequency detector and charge pump replacement in all-digital PLL (ADPLL) and is based on a pseudodifferential digital architecture that is insensitive to nMOS and pMOS transistor mismatches.
A DTC-based fractional-N ADPLL is described in an article by Nenad Pavlovic & Jos Bergervoet, ISSCC2011, Session 3, RF Techniques, 3.2, 2011 IEEE International Solid-State Circuits Conference, ISBN: 978-1-61284-302-5/11. The DTC-based ADPLL has a control loop that updates the DCO frequency so that the DCO phase, measured by counting the DCO clock edge transitions, follows the reference phase produced by accumulating the frequency control word on each reference clock cycle. The DTC is added to lower the quantization noise in the fractional-N mode and is implemented by a digitally-controlled delay line.
While DTC implementations can be capacitor based with switched capacitors controlling the delay, linearity and noise are factors that can affect the efficiency of such implementations.